Boreal firmware architecture revision
- System Core:
- Processing systems (Zynq7000 , Zynq MPSoC) are implemented in block designs and wrapped into sys_core with generate statements based on the chosen board
- Common Core:
- Common feature such as USR_ACCESS2 fw_id block are included into a block design that is instantiated in the cmn_core
- User Core:
- Users will have to create a device specific block design and integrate it into the usr_core wrapper with a dedicated generate statement for the instantiation.
- Boreal Top:
- Top module that wraps the System, Common and User cores. It offers a single top level interface to both supported boards.
The System Core provides one AXI3 interface to the Common Core and another one to the User Core. Each have fixed address maps to allow for a unified implementation accross users. This way an AXI interconnect is used in the Common Core and can be used in the User Core in order to give access to additional AXI4Lite interfaces.
A register map IP wraps the register interface and the axi4lite slave interface in a compact implementation giving access to input and output data, with a configurable number of registers.
Simulation of the axi4lite slave interface, the register interface and the register map is successfully performed using cocotb.
Bitfile successfuly generated for both ZC706 and ZCU102 using the LED blinking pilot project. The latter will be tested on the boards using Peary for the LED blinking control.
